Semiconductor devices are usually either connected by means of an interposer substrate in a BGA (Ball Grid Array) on a printed circuit board or else the semiconductor device is connected directly on the printed circuit board as a WLP/CSP (Wafer Level Package/Chip Size Package).
In the case of a conventional BGA arrangement according to FIG. 4, a semiconductor device 10 is connected by means of solder balls 30 and a mechanical connecting device 31 to an interposer substrate 32 or a base. To protect the semiconductor device 10, it is surrounded by a cladding 33. Solder balls 30 serve in turn for the electrical bonding of the interposer substrate 32 onto a printed circuit board 34. As illustrated in FIG. 4 by the projection of an enlargement in the large oval, the bonding or the wiring takes place in or on the interposer substrate 32 by interconnects 35, for example of copper, which generally have a width of more than 100 μm and a height or thickness of more than 20 μm in the case of the printed circuit board technology illustrated. As a result, good electrical connection with low interconnect resistance is ensured, although this results in a high overall volume or large outer dimensions of the arrangement.
In FIG. 5, on the other hand, a conventional WLP/CSP arrangement is shown. In this case, the semiconductor device 10 or the semiconductor chip is connected by means of solder balls 30 directly to the printed circuit board 34. As in FIG. 4, in FIG. 5 the large oval is used to illustrate a detail of an enlargement, in which the semiconductor device 10 or the chip is represented with underlying electrical terminal contact devices 12. These contact or wiring devices 12 generally have a width of more than 20 μm and a height of approximately 2 to 4 μm, which are applied [sic] using thin-film technology.
Although the arrangement according to FIG. 5 allows a more compact construction without the additional interposer substrate, with this arrangement there is a disadvantage in that the conductivity of the wiring device of the WLP/CSP is lower by a factor of 5 to 10 than the conductivity of a conventional BGA with an interposer according to FIG. 4. In the case of a WLP arrangement, the resistance of the wiring device is high in comparison with the BGA alternative, for which reason the performance capability of the arrangement or the package is restricted, in particular in the case of high-frequency applications.
Represented in FIG. 6 is the cross section of a conventionally produced semiconductor device with a contact or wiring device. On a semiconductor substrate 10 of a chip or wafer there is firstly applied a carrier layer 11, preferably of titanium or a titanium compound, which is adjoined by a conductive layer 12 or interconnect level, for example comprising copper. The conductive layer 12 is followed by a barrier layer 40, which comprises nickel in particular and prevents metal atoms, for example gold, of a protective layer 41 applied on top of it from diffusing into the conductive layer 12, for example of copper.
Such an interconnect device protected from above, for example as a contact or wiring device of a semiconductor device 10, is applied by various production steps involving sputtering and/or electrochemical depositing processes and structured by an etching process with a photochemically structured photomask. The height of such a sequence of layers is usually approximately 4 to 6 μm. Disadvantages of such an arrangement are not only the multiple layer generating processes, which cause expenditure of time and consequently costs, but also those attributable to the fact that the side walls of the layer arrangement of the semiconductor substrate 10 are not protected and are consequently exposed in particular to electrochemical corrosion. In particular, the laterally exposed conductive layer 12, preferably of copper, is exposed to corrosion, the individual layers forming a galvanochemical element, which has a tendency to undergo undesired chemical reactions.
The necessary layers and method steps for the production of such a terminal or wiring device are generally sputtering on of an adhesive or carrier layer 11, sputtering on of a copper carrier layer (not represented), carrying out of a photolithographic process for the structuring of the sputtered-on metallizations 11, depositing of a copper interconnect layer 12, depositing of a nickel layer as a barrier or buffer layer 40, depositing of a gold layer 41 as protection and, finally, removal of the structured photomask and etching of the carrier layer in regions in which the structured photomask was previously provided.
In such a sequence of layers, the conductivity is determined by the deposited or plated copper layer 12. An improvement in the conductivity means increasing the depositing or plating time, which is associated directly with the process or production costs. To realize the same high conductivity as in the case of a BGA connection according to FIG. 4, which has an interposer 32 or base, the depositing or plating costs for a CSP/WLP terminal or wiring device as illustrated in FIG. 6 or FIG. 5 would not be economical.